1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and manufacturing method thereof, and more particularly, to a flash memory device and manufacturing method thereof.
2. Description of the Related Art
Flash memory devices are classified generally as read only memory (ROM), and unlike random access memory (RAM) devices, they have non-volatility in which data stored in a memory cell can be retained when the power supply is removed. Flash memory devices also allow for high integration, so they are widely used in computer memory cards, etc. Unit cells of flash memory devices have basically the same structure as memory cells of other programmable ROM devices such as erasable programmable ROM (EPROM) or electrically erasable programmable ROM (EEPROM). Each unit cell of a flash memory device includes a cell transistor, that is, a tunnel oxide layer, a floating gate electrode, an intergate dielectric layer, and a control gate, which serves as a word line, all of which are sequentially stacked on a channel region.
FIG. 1 is a plan view showing the main portion of a cell array in a conventional flash memory device. FIG. 2 is a cross sectional view taken along line A-Axe2x80x2 of FIG. 1, based on FIGS. 1 and 2D disclosed in Japanese Patent Hei 6-188431. Referring to FIGS. 1 and 2, a field oxide layer 14 for isolating an active region, in which a device is formed, as well as the devices themselves, formed on a silicon substrate 10. Then, a gate oxide layer 12 is interposed to form a floating gate electrode 16 comprised of polysilicon, on top of which a dielectric layer 23 is interposed to form a control gate electrode 24 comprised of polysilicon continuously run in a plurality of memory devices. The dielectric layer 23 is, e.g., an oxide-nitride-oxide (ONO) layer having two oxide layers 18 and 22 sandwiching a nitride layer 20.
Referring to FIGS. 1 and 2, a memory device in the nonvolatile semiconductor memory device is arranged as follows. Active regions (not shown) of the device extend parallel to one another between the adjacent field oxide layers 14 along the longitudinal direction of the FIG. 1. The gate oxide layer 12, which is formed sufficiently thin to permit a charge tunneling, is interposed to form floating gate electrodes 16 in each unit cell of the memory device in a direction perpendicular to the active region The floating gate electrodes 16 are separated from one another on the field oxide layer 14. The dielectric layer 23 is interposed on the separated floating gate electrode 16 to form the control gate 24 continuously run in a plurality of unit cells in the same direction to the floating gate electrode 16. The control gate electrode 24 serves as a word line of the memory device, and only two word lines are arranged to cross each field oxide layer 14 in FIG. 1.
Meanwhile, a bit line (not shown) goes over the active region, both of which are electrically connected through a contact 28 exposing the surface of the active region. A unit cell transistor is formed at the intersecting portion of the control gate electrode 24, which is a word line, and the active region. Reference numeral 30 denotes a drain region, which is formed in common between adjacent two unit cells, and reference numeral 32 denotes a source region. Reference numeral 26 denotes a separation region which separates the field oxide layers 14 and channel regions, respectively.
As shown in FIG. 2, the floating gate electrode 16 in the nonvolatile flash memory device is etched only on the field oxide layer 14 and separated from the adjacent floating gate electrodes 16 in the unit cell. The floating gate electrodes 16 have the same pattern within the memory cell of the nonvolatile memory device and are repetitively formed in each unit cell. The floating gate electrodes 16 are formed in such a way as to provide a sufficient coupling ratio (C/R). The coupling ratio is used for estimating the quantity of charges accumulated or removed after having been transmitted from a channel region of the silicon substrate 10 to these floating gate electrodes 16 via a gate oxide layer 12 by quantum-mechanical tunneling in each unit cell transistor.
FIG. 3 is a graph of illustrating relationship between a space critical dimension (CD) and a coupling ratio between adjacent floating gate electrodes in a conventional flash memory device. A space CD between the adjacent floating gate electrodes represents a distance between adjacent floating gate electrodes to be separated from each other on the field oxide layer. As the space CD is increased, the length of the floating gate is reduced, and accordingly, a coupling ratio is reduced. Conversely, as the space CD is reduced, the length of the floating gate is increased and a coupling ratio is increased. It can be seen from FIG. 3 that a space CD is inversely proportional to coupling ratio. Therefore, in order to secure a sufficient coupling ratio, a space CD must be maintained below a predetermined value.
FIG. 4 illustrates another problem that may occur if a space CD between the floating gate electrodes is large in the conventional nonvolatile flash memory device. More specifically, during the manufacture of a nonvolatile flash memory device, a gate oxide layer 12 is interposed on a substrate 10 to form a floating gate electrode 16 pattern, and then an intergate dielectric layer 23 is interposed on the entire surface of the substrate 10 to form a control gate electrode (not shown). In this case, in order to remove the ONO dielectric layer 23 formed on the sidewalls of the floating gate electrode 16, an etching target is increased, to etch and consume the field oxide layer 14 corresponding to about a thickness xe2x80x9cH2xe2x80x9d of the floating gate electrode 16 to a depth xe2x80x9cH3xe2x80x9d, e.g., to a thickness of at least 800 xc3x85.
Thus, as shown in FIG. 4, if the space CD xe2x80x9cL3xe2x80x9d between the adjacent floating gate electrodes 16, which are electrically separated from each other on the field oxide layer 14, is large, a difference between the space CD xe2x80x9cL3xe2x80x9d and a length xe2x80x9cL2xe2x80x9d corresponding to a ridge portion of the field oxide layer 14, the thickness of which is maintained uniform as xe2x80x9cH1xe2x80x9d, is small, so that a margin against misalignment is not sufficiently provided in a photolithography process. For example, if misalignment occurs in a photolithography process for forming the floating gate electrode 16, a position on the field oxide layer 14, in which a material for the floating gate electrode 16 is etched, may be located on the edges of the field oxide layer 14 deviating from the ridge portion thereof. In this case, as described in the foregoing, because the field oxide layer 14 is consumed together in etching the ONO dielectric layer 23, the field oxide layer is almost removed on the edges thereof having a relatively small thickness, which significantly weakens isolation. Reference character xe2x80x9cL1xe2x80x9d in FIG. 4 denotes a horizontal distance of the field oxide layer 14.
As described above, in a process of forming a floating gate electrode in a nonvolatile flash memory device, a reduction in a space CD between floating gate electrodes is essentially required, for which the following conventional methods have been used.
FIGS. 5-11 are cross sectional views showing an example for a process of forming the floating gate electrode of the conventional flash memory device. Firstly, referring to FIG. 5, a filed oxide layer 14 and a gate oxide layer 12 are provided over a substrate 10 comprised of a semiconductor material such as silicon using a local oxidation of silicon (LOCOS) process which is widely known as an isolation method. After a floating gate electrode material 16 comprised of polysilicon, a first silicon nitride layer 40, and a first polysilicon layer 42 are sequentially formed on the entire surface of the substrate 10, a photoresist pattern 44a is formed by a usual photolithography technique.
Next, as shown in FIG. 6, a first polysilicon pattern 42a is formed by an etching process that uses the photoresist pattern 44a as an etching mask, and the residual photoresist pattern 44a is then removed as shown in FIG. 7. Subsequently, as shown in FIG. 8, a second polysilicon layer 46 is provided over the entire surface of the substrate 10, and blanket etchback of the second polysilicon layer 46 is performed to form second polysilicon spacers 46a on the sidewalls of the first polysilicon pattern 42a, as shown in FIG. 9. Then, using the second polysilicon spacers 46a as an etching mask, the exposed first silicon nitride layer 40 is etched to form a first silicon nitride pattern 40a. 
For a subsequent process, a blanket etching process is performed to etch the floating gate electrode material 16 exposed by the first silicon nitride pattern 40a. In this case, the first polysilicon pattern 42a and the second polysilicon spacers 46a, which remain on the first silicon nitride pattern 40a, are etched together to leave a floating gate electrode 16a and the first silicon nitride pattern 40a. Next, the first silicon nitride pattern 40a is removed by phosphoric acid strip, thereby forming the final floating gate electrode 16a as shown in FIG. 11.
In the conventional method as above, since the second polysilicon spacers 46a are used as an etching mask, after development inspection (ADI) space CD measured with respect to the photoresist pattern 44a, which is formed after a developing process, is about 0.25 xcexcm. However, after cleaning inspection (ACI) space CD, which is measured after forming the final floating gate electrode 16a, can be significantly reduced, thereby providing a sufficient coupling ratio and a sufficient process margin for the aforementioned misalignment.
However, the conventional method requires five deposition steps and three etching steps from the time when the floating gate electrode material 16 is formed on the substrate 10 underlying the field oxide layer 14 until when the final floating gate electrode 16a is formed. Thus, the processes are so complicated and require a long time, thereby increasing the manufacturing cost to drop a product yield rate. Furthermore, as shown in FIG. 11, because the sidewalls of the floating gate electrode 16a separated on the field oxide layer 14 are made vertical, in subsequent processes, i.e.,ONO dielectric layer formation step and an etching process, the field oxide layer 14 is consumed to a thickness approximately corresponding to a thickness of the floating gate electrode 16a. Thus, as described above, if misalignment occurs, there is danger of greatly weakening isolation by the field oxide layer 14.
FIGS. 12-15 are cross sectional views showing another example of a process of forming a floating gate electrode in the conventional flash memory device. Initially, referring to FIG. 12, similarly as shown in FIG. 5, a field oxide layer 54 and a gate oxide layer 52 are formed on a substrate 50 comprised of a semiconducting material such as silicon by a LOCOS process which is a well-known isolation technique. After a floating gate electrode material 56 comprised of polysilicon, an anti-reflection layer 58 comprised of a silicon nitride layer are sequentially formed over the entire surface of the substrate 50, a photoresist pattern 60a is formed by a usual photolithography technique.
Next, as shown in FIG. 13, an anti-reflection pattern 58a and the underlying floating gate electrode 56a are formed by an etching process which uses the photoresist pattern 60a as an etching mask, and the residual photoresist pattern 60a is then removed by ashing/strip process. Subsequently, as shown in FIG. 14, a third polysilicon layer 62 is formed on the entire surface of the substrate 50, and then as shown in FIG. 15, blanket etchback of the third polysilicon layer 62 is performed to form third polysilicon spacers 62a along the sidewalls of the floating gate electrode 56a. Next, if the residual anti-reflection pattern 58a is removed, then the floating gate electrode 56a, on the sidewalls of which the third polysilicon spacers 62a are attached, are formed.
The conventional method above has an advantage in that a sufficient coupling ratio and a sufficient process margin for misalignment can be secured, because a space CD between the adjacent floating gate electrodes can be significantly reduced by using the third polysilicon spacers 62a. Furthermore, this method can greatly simplify a process. However, since a pattern of the floating gate electrode 56a comprised of polysilicon is exposed after it has been formed by an etching process, an oxide layer (not shown) can be formed on the exposed surface. Furthermore, since the third polysilicon layer 62 is formed on the oxide layer in a subsequent step of FIG. 14, the oxide fence, which is an insulating material, remains on the final floating gate electrode 56a, thus deteriorating electrical characteristics such as storage capacity of the floating gate electrode 56a. 
To address the above limitations, it is an objective of the present invention to provide a nonvolatile semiconductor memory device having a shape which is capable of reducing a space critical dimension (CD) between adjacent floating gate electrodes separated on a device isolation layer as well as reducing consumption (etching-away) of the device isolation layer during etching of a dielectric layer formed on the floating gate electrode.
It is another objective to provide a method of manufacturing a nonvolatile semiconductor memory device capable of reducing a space CD between adjacent floating gate electrodes separated on a device isolation layer by a simplified process as well as reducing consumption of the device isolation layer in etching a dielectric layer formed on the floating gate electrode.
Accordingly, in order to achieve the first objective, the present invention provides a nonvolatile semiconductor memory device that includes a semiconductor substrate, a plurality of floating gate electrodes separated over the semiconductor substrate by interposing a gate insulating layer. The floating gate electrodes are separated in a device isolation region for isolating a plurality of memory cells arranged on the semiconductor substrate, and the end portions of the floating gate electrode, which are separated to oppose each other, have a step pattern.
The present invention also provides a nonvolatile semiconductor memory device that includes a semiconductor substrate, a plurality of floating gate electrodes which are formed separated over the semiconductor substrate, interposing a gate insulating layer. The floating gate electrodes are separated on a device isolation region for isolating a plurality of memory cells arranged on the semiconductor substrate, and the end portions of the floating gate electrode, which are separated to oppose each other, horizontally extend over the surface of the device isolation region, and includes projected portions having a rounded step pattern and overlying spacers having a round pattern continued from the round pattern of the projected portions, which are disposed between the projected portions and the sidewalls of the floating gate electrode.
In order to achieve the second objective, the present invention provides a method of manufacturing a nonvolatile semiconductor memory device that includes the steps of: forming a plurality of device isolation regions on a semiconductor substrate; forming a gate insulating layer on the entire surface of the semiconductor substrate; forming a floating gate electrode material on the entire surface of the resulting material; forming a photoresist pattern on the floating gate electrode material so that a portion of the floating gate electrode material overlying the device isolation region may be exposed; performing a first etch on the floating gate electrode material to a predetermined depth, using the photoresist pattern as an etching mask; forming polymer spacers on the etched sidewalls of the photoresist pattern and the floating gate electrode material; and performing a second etch on the floating gate electrode material so that the floating gate electrode material may be separated, using the photoresist pattern and the polymer spacers as an etching mask.
The present invention also provides a method of manufacturing a nonvolatile semiconductor memory device that includes the steps of: forming a plurality of device isolation regions on a semiconductor substrate; forming a gate insulating layer on the entire surface of the semiconductor substrate; forming a floating gate electrode material on the entire surface of the resulting material; forming an anti-reflection layer on the floating gate electrode material; forming a photoresist pattern on the floating gate electrode material so that a portion of the floating gate electrode material overlying the device isolation region may be exposed; performing a first etch on the floating gate electrode material to a predetermined depth, using the photoresist pattern as an etching mask; removing the photoresist pattern; forming a spacer material on the resulting material; etching back the spacer material to form spacers on the sidewalls of the floating gate electrode material undergoing the first etch; and performing a second etch on the floating gate electrode material so that the floating gate electrode material may be separated, using the residual anti-reflection layer and the spacers as an etching mask.
The present invention also provides a method of manufacturing a nonvolatile semiconductor memory device that includes the steps of: forming a plurality of device isolation regions on a semiconductor substrate; forming a gate insulating layer on the entire surface of the semiconductor substrate; forming a floating gate electrode material on the entire surface of the resulting material; forming an anti-reflection layer on the floating gate electrode material; forming a photoresist pattern on the floating gate electrode material so that a portion of the floating gate electrode material overlying the device isolation region may be exposed; performing a first etch on the floating gate electrode material to a predetermined depth, using the photoresist pattern as an etching mask; removing the photoresist pattern; forming a conductive material on the entire surface of the resulting material; and performing a second etch by etching back the conductive material and the underlying floating gate electrode material to separate the floating gate electrode material from one another.
Accordingly, the present invention can realize a nonvolatile semiconductor memory device which is capable of providing a sufficient coupling ratio by significantly reducing a space CD between adjacent floating gate electrodes since the sidewalls of floating gate electrode have a step or rounded spacer pattern while providing a sufficient process margin so that degradation in isolation due to misalignment can be prevented during a photolithography process.
Furthermore, the present invention can significantly reduce a space CD since the sidewalls of a floating gate electrode material can be formed by a second etching process to have a step or round spacer pattern, while securing a sufficient process margin so that degradation in isolation due to misalignment can be prevented during a photolithography process.